If at First
The Successive Approximation Register
The Successive Approximation Register
During routine office visits with my physician, the assistant asks me to step on the scale. Every assistant sets the scale to a maximum of two hundred pounds and then proceeds to dial in my weight. I’ve begun to keep track of how long it takes each assistant to realize the scale needs to be set to the next higher range. This process of estimating a value, comparing the estimate to the value, and adjusting the estimate is the heart of the Scientific Method. The successive approximation method used by analog-to-digital converters (ADCs) follows precisely this prescription.
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The successive approximation register (SAR) of an ADC consists of a digital-to-analog converter (DAC) and a comparison circuit (comparitor). An initial guess at the correct n-bit binary representation of the input voltage is made and is converted to an analog voltage by the n-bit DAC. The DAC voltage and the input voltage are compared and the comparitor reports “too high” or “too low”. In response, the SAR adjusts the value of the binary guess in the direction indicated and the cycle repeats. After the appropriate n-bit pattern is found, it is reported as the output of the ADC. There are many search methods used to find the appropriate answer, but each method requires a finite amount of search time that increases as the resolution (number of bits) of the ADC increases. A 16-bit successive approximation ADC requires 200 ns of search time, resulting in a maximum sampling rate of 5 MHz.
To increase the maximum sampling rate, a fundamentally different search method was developed. Imagine that my physician’s office purchased a row of 256 identical scales and that, starting with zero pounds, each scale was set to one pound higher than the previous scale. Also picture a lever mechanism that permits me to step on all of the scales simultaneously. In a single measurement my weight can be deduced by finding the point in the line of scales where they switch from a reading of “heavier-than” to “lighter-than”. Each possible value from 0 to 255 lbs would be tested in parallel. Parallel ADCs contain an array of comparitors that are referenced to each possible voltage value. These “Flash ADCs” are so named for their rapid speed of conversion in comparison to their successive approximation cousins. Unfortunately, the digital logic requires (2 to the n-bits power minus one) comparitors to make the conversion. Therefore at 8-bit and 10-bit Flash ADCs require 255 and 1023 comparitors, respectively. This large density of comparitors limits the time-constant of the Flash ADC circuit to around 10 ns and therefore the sampling rate to ca. 100 MHz.
In 1990, National Semiconductor patented the sub-ranging parallel comparitor or “sub-ranging Flash ADC”. This device separates the total number of bits into the most-significant (MSBs) and the least-significant (LSBs). For example, an 8-bit conversion can use one 4-bit Flash ADC for the MSBs and a second 4-bit Flash ADC for the remaining LSBs. This reduces the number of required comparitors to 30. The MSB values are “flashed” in a single step and the resulting bit pattern is sent through an 8-bit DAC. The DAC output is subtracted from the input value and the remaining voltage is flashed to obtain the remaining 4 LSBs. The smaller time constant of the 30 comparitors requires only 1 ns to make the conversion, resulting in a maximum sampling rate of 1 GHz.
Another method of ADC that is specifically designed for the high-resolution measurement of time-varying signals is to make a conversion initially and subsequently track the change in this value. This method only requires a 1-bit DAC that is used to add or subtract the voltage step of the LSB from the total comparitor voltage as the input voltage varies. Known as a Sigma Delta ADC, the 1-bit resolution of the DAC introduces “quantization noise” into the signal. This random noise is produced when the actual analog signal lies between the two nearest digital levels. A common technique for increasing the signal-to-noise ratio (SNR) of signals containing random noise is to obtain the average of replicate measurements. These replicates are obtained by operating the Sigma Delta ADC at “oversampling” rates greater than 64 times the Nyquist frequency. When viewed in the frequency domain, the finite amount of quantization noise is spread over the full input bandwidth of the Sigma Delta ADC. After these higher frequencies are digitally filtered, only a fraction remains in the actual low-frequency measurement. Sigma Delta ADCs currently have a maximum resolution of 18 bits and their actual sampling rate is limited to ca. 200 kHz due to the required high rate of oversampling.
National Instruments recently patented a new ADC technology known as the Flexible Resolution ADC (Flex ADC) capable of delivering 21-bit resolution at 10 kHz, 14-bits at 1 MHz, and 8-bits at 100 MHz. Flex ADC is based on a single-step 8-bit Flash ADC operating at 100MHz that is part of a Sigma Delta circuit. At 100 MHz, the 8-bit ADC operates in true “flash” mode. As the frequency of the input signal decreases, the 100-MHz oversampling permits the ADC to take advantage of the Sigma Delta topology, and increase the resolution to a maximum of 21-bits at frequencies lower than 10 kHz. Advanced high-speed digital signal processor (DSP) circuits are the critical technologies that make the Flex ADC possible. The DSPs permit the different noise and linearity profiles of the Flash and Sigma Delta methods to be combined into a hybrid ADC. As the digital communication revolution continues at its brisk pace the nature and performance of the next ADC development is anybody’s guess.
This material originally appeared as a Contributed Editorial in Scientific Computing and Instrumentation 17:11 October 2000, pg. 14.
William L. Weaver is an Associate Professor in the Department of Integrated Science, Business, and Technology at La Salle University in Philadelphia, PA USA. He holds a B.S. Degree with Double Majors in Chemistry and Physics and earned his Ph.D. in Analytical Chemistry with expertise in Ultrafast LASER Spectroscopy. He teaches, writes, and speaks on the application of Systems Thinking to the development of New Products and Innovation.